********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 19, 2014
*ECN S14-1062, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8802DB D G S 
M1 3 GX S S NMOS W= 286660u L= 0.25u 
M2 S GX S D PMOS W= 286660u L= 3.348e-07 
R1 D 3 3.825e-02 2.670e-03 4.103e-07 
CGS GX S 2.360e-10 
CGD GX D 2.142e-11 
RG G GY 3.5 
RTCV 100 S 1e6 7.171e-05 2.125e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.3e-8 
+ RS = 7.600e-04 KP = 4.978e-05 NSUB = 2.242e+17 
+ KAPPA = 1.000e-06 ETA = 8.353e-04 NFS = 2.145e+12 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.3e-8 
+NSUB = 3.260e+17 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.013e-08 TREF = 25 BV = 9 
+RS = 1.000e-01 N = 1.346e+00 IS = 2.859e-08 
+EG = 7.483e-01 XTI = 2.034e-01 TRS = 4.563e-04 
+CJO = 1.689e-10 VJ = 4.576e-01 M = 2.812e-01 ) 
.ENDS 
